Download Section (Free/Publicly available):- Hardware Security Tools for Hardware Accelerators/ IP cores

Click here for accessing the readme file - "How to create the input application file format for all the tools": Sample demonstration given for 8-point DCT application



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(1) Faciometric Hardware Security Tool Click here for tool download

Click here to view the high-resolution tool GUI image



Summary and Threat Model  :Dr. Sengupta and his team have developed a Faciometric hardware security tool to simulate and analyse the functionality of facial biometric based approach for securing DSP hardware accelerators against piracy and false claim of ownership threats.
Objective of the toolThe left portion of the tool shows the panel for providing required inputs to the tool, right portion shows the panel with output buttons to see the intermediate and final outputs of the facial biometric based hardware security approach. The panel in the middle shows the status of the intermediate steps (i.e. capture facial biometric with required grid size, generate nodal points and facial features set, calculation of feature dimensions for selected features, facial signature generation and conversion to hardware security constraints) in generating hardware security constraints from a captured/input facial image. Initially, these status bars remain Red. Upon applying the inputs, the respective status bar turns Green. The Faciometric hardware security tool accepts the DSP application input in the form CDFG along with the resource constraints. The tool shows all the intermediate steps of facial biometric based hardware security approach and the finally generated facial signature and corresponding hardware security constraints at the output. Further, it also shows scheduling and registers allocation pre and post embedding facial signature constraints, onto the output window. The embedded facial signature in the hardware accelerator design can be used as a unique digital evidence to secure against piracy and false claim of ownership threats.

Click here for accessing The video tutorial of the tool   Click here for accessing The database required for facial image input

Supporting IEEE Publications:
A. Sengupta and M. Rathor, "Facial Biometric for Securing Hardware Accelerators," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 1, pp. 112-123, Jan. 2021, doi: 10.1109/TVLSI.2020.3029245



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(2) Crypto-stego tool -: Crypto-steganography tool Click here for tool download

Click here to view the high-resolution tool GUI image



Summary and Threat Model : Dr. Sengupta and his team have developed a Crypto-Stego tool to simulate and analyse the functionality of crypto-based steganography approach for securing DSP hardware accelerators against piracy and false claim of ownership threats.
Objective of the tool: The left portion of the tool shows the panel for providing required inputs to the tool, right portion shows the panel with output buttons to see the intermediate and final outputs of the crypto-based steganography approach. The panel in the middle shows the status of the key-driven steps (i.e. state matrix formation, row diffusion, Trifid cipher, alphabet substitution and byte concatenation) of the crypto-based steganography approach. Initially, these status bars remain Red. Upon applying the stego-key, the respective status bar turns Blue. The Crypto-Stego tool accepts the DSP application input in the form CDFG along with module library and resource constraints. The tool shows all the intermediate steps of crypto-based steganography and the finally generated stego-constraints at the output. Further, it also shows scheduling and registers allocation pre and post embedded steganography constraints, onto the output window. The embedded steganography constraints in the hardware accelerator design can be used as digital evidence to secure against piracy and false claim of ownership threats.

Click here for accessing chapter 2 of the IET book on "Secured hardware accelerators for DSP and image processing applications" where details of the tool are provided

Supporting IEEE Publications:

1. Anirban Sengupta, Mahendra Rathor "IP Core Steganography for Protecting DSP Kernels used in CE Systems", IEEE Transactions on Consumer Electronics (TCE) , Volume: 65 , Issue: 4 , Nov. 2019, pp. 506 - 515


2. Anirban Sengupta, Mahendra Rathor "Structural Obfuscation and Crypto-Steganography based Secured JPEG Compression Hardware for Medical Imaging Systems", IEEE Access, Volume: 8, Issue:1, Dec 2020, pp. 6543-6565


3. Mahendra Rathor, Anirban Sengupta "Design Flow of Secured N-point DFT Application Specific Processor using Obfuscation and Steganography", IEEE Letters of the Computer Society (LOCS) , Volume: 3 , Issue: 1 , June 2020, pp. 13 - 16.


4. Anirban Sengupta, Mahendra Rathor "Crypto based Dual phase Hardware Steganography for Securing IP cores", IEEE Letters of the Computer Society (LOCS) , 2019, Volume 2 , Issue 4, pp. 32-35






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(3) KHC-Stego tool -: Key-triggered Hash-chaining Driven Steganography tool Click here for tool download

Click here to view the high-resolution tool GUI image



Summary and Threat Model : Dr. Sengupta and his team have developed a KHC-Stego tool to simulate and analyse the functionality of key-triggered hash-chaining driven steganography approach for securing DSP hardware accelerators against piracy and false claim of ownership threats.
Objective of the tool:The left portion of the tool shows the panel for providing required inputs to the tool, right portion shows the panel with output buttons to see the intermediate and final outputs of the key-triggered hash-chaining based steganography approach. The panel in the middle shows the status of the intermediate steps viz. CDFG scheduling of DSP application, encoding selection, executing hash-chaining process and insert constraints. Initially, these status bars remain red. Upon applying the inputs, the respective status bar turns green. The KHC-Stego tool accepts the DSP application input in the form CDFG along with module library and resource constraints. The tool shows output of intermediate steps of key-triggered hash-chaining based steganography, finally generated stego-constraints, the security metric in terms of probability of coincidence, pre and post-steganography design cost. Further, it also shows scheduling and registers allocation pre and post-embedding steganography constraints, onto the output window. The embedded steganography constraints in the hardware accelerator design can be used as digital evidence to secure against piracy and false claim of ownership threats.

Click here for accessing chapter 7 of the IET book on "Secured hardware accelerators for DSP and image processing applications" where details of the tool are provided

Supporting IEEE Publications:

1. Anirban Sengupta, Mahendra Rathor "IP Core Steganography for Protecting DSP Kernels used in CE Systems", IEEE Transactions on Consumer Electronics (TCE) , Volume: 65 , Issue: 4 , Nov. 2019, pp. 506 - 515






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(4) KSO-PW tool -: Key-driven structural obfuscation and physical level watermarking tool Click here for tool download

Click here to view the high-resolution tool GUI image



Summary and Threat Model : Dr. Sengupta and his team have developed a KSO-PW tool to simulate and analyse the functionality of Key-driven structural obfuscation and physical level watermarking approach for securing DSP hardware accelerators against reverse engineering, piracy and false claim of ownership threats.
Objective of the tool: The left portion of the tool shows the panel for providing required inputs to the tool, right portion shows the panel with output buttons to see the intermediate and final outputs of the structural obfuscation and physical level watermarking based double line of defence approach. The panel in the middle shows the buttons for entering secret SO-keys (for multiple structural transformation techniques viz. loop unrolling, partitioning, ROE, THT and folding-knob) and vendor’s signature for watermarking. Since ROE is not applicable for FIR application, therefore the button for entering the ROE key input remains invisible. It is noteworthy in the GUI of KSO-PW tool that for a DSP application, only those secret key-buttons are activated for which the corresponding structural transformation techniques are applicable. The KSO-PW tool accepts the DSP application input in the form CDFG along with module library file and resource constraints file. The tool shows outputs of all intermediate steps of structural obfuscation and watermarking approach and finally generated watermarked floorplan of the obfuscated design. Further it also shows design cost before performing structural obfuscation and watermarking (i.e. baseline design cost), design cost after intermediate steps and the final design cost.

Click here for accessing chapter 4 of the IET book on "Secured hardware accelerators for DSP and image processing applications" where details of the tool are provided

Supporting IEEE Publications:

1. Anirban Sengupta, Mahendra Rathor "Enhanced Security of DSP circuits using Multi-key based Structural Obfuscation and Physical-level Watermarking for Consumer Electronics systems", IEEE Transactions on Consumer Electronics (TCE) , Volume: 66, Issue:2, May 2020, pp. 163-172


2. Anirban Sengupta, Mahendra Rathor, Somesh Patil, Naukudkar Gaurav Harishchandra "Securing Hardware Accelerators using Multi-Key based Structural Obfuscation", IEEE Letters of the Computer Society (LOCS) , Volume: 3, Issue:1, June 2020, pp. 21-24.






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(5) POM-SO tool -: Pseudo operation mixing based structural obfuscation tool Click here for tool download

Click here to view the high-resolution tool GUI image



Summary and Threat Model : Dr. Sengupta and his team have developed a POM-SO tool (pseudo operation mixing based structural obfuscation tool) to simulate and analyse the pseudo operation mixing based obfuscation approach for securing DSP hardware accelerators against reverse engineering (and Trojan insertion).
Objective of the tool: The left portion of the tool shows the panel for providing required inputs to the tool and right portion shows the panel to see the intermediate and final outputs of the pseudo operation mixing based structural obfuscation approach. The POM-SO tool accepts the DSP application input in the form CDFG along with module library and resource constraints. The tool shows intermediate steps of pseudo operation mixing and finally generated structurally transformed scheduled and resource allocated DFG at the output. This output can be used to generate a structurally obfuscated RTL design of a DSP application which is un-obvious to an attacker and can hinder reverse engineering.

Click here for accessing chapter 9 of the IET book on "Secured hardware accelerators for DSP and image processing applications" where details of the tool are provided

Supporting IEEE Publications:

1. Mahendra Rathor, Anirban Sengupta, "Obfuscating DSP Hardware Accelerators in CE Systems Using Pseudo Operations Mixing", IEEE International Conference on Zooming Innovation in Consumer Electronics 2020 (ZINC 2020) , Serbia, Accepted, May 2020






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