M-HLS: Malevolent High Level Synthesis for Watermarked Hardware IPs View

A Survey of High Level Synthesis Based Hardware Security Approaches for Reusable IP Cores View

Time-Bomb HLS Trojan for Performance Degradation Payload View

Triple-Phase Watermarking for Reusable IP Core Protection During Architecture Synthesis View

Hardware Watermarking and IP Metering for IP Core Protection View

Hardware Security of Digital Image Filter IP Cores using IP Seller’s Fingerprint Encrypted Amino Acid Biometric View

Paradigms of Hardware Security for Addressing Threats of IP Piracy and Trojan during High Level Synthesis View

Hardware Security, IP Core Protection and High Level Synthesis (HLS) View

A Survey of High-Level Synthesis-Based Hardware (IP) Watermarking Approaches View

Watermarking of Transient Fault Detectable IP Designs using Multivariate Encoded HLS Scheduling based Security View

Designing Low Cost Secured DSP Core using Steganography and PSO for CE systems View

IP Core Protection of Image Processing Filters With Multi-Level Encryption and Covert Steganographic Security View

Low-Cost Hardware Security of Laplace Edge Detection and Embossment Filter Using HLS Based Encryption and PSO View

Forensic Detective Control using Hardware Steganography for IP Core Protection View

Forensic Detective Control using Digital Signature based Watermark for IP Core Protection View

Protecting Right of an IP Buyer using Cryptosystem based Multi-variable Fingerprinting View

Security of Functionally Obfuscated DSP cores View

Robust Digital Signature to Secure IP Core against Fraudulent Ownership and Cloning View

Secured and Optimized Hardware Accelerators Using Key-Controlled Encoded Hash Slices and Firefly Algorithm Based Design Space Exploration View

Fusing IP Vendor Palmprint Biometric with Encoded Hash for Hardware IP Core Protection of Image Processing Filters View

HLS Design Methodology of Optimized and Secured Hardware IPs View

Secure FFT IP using C way Partitioning based Obfuscation and Fingerprint View

Structural Obfuscation and Crypto-Steganography-Based Secured JPEG Compression Hardware for Medical Imaging View

HLS Watermarking of Blur, Embossment and Sharpening Filters Using Fused Ocular Biometrics and Digital Signature View

Revisiting Black-Hat HLS: A Lightweight Countermeasure to HLS-Aided Trojan Attack View

Secure and Optimized IP design using Cipher-Based Multi-layer Encrypted HLS Watermarking integrated with FA-DSE View

HLS driven Hybrid GA-PSO for Exploration of Optimal Palmprint Biometric based IP Watermark and Loop Unrolling View

HLS-based Hardware Watermarking View

Fault Secured JPEG-Codec Hardware Accelerator design View

Securing Reusable Hardware IP cores using Palmprint Biometric View

Security-Design cost Tradeoff for Low-cost Hardware Design View

SWIFT: Swarm Intelligence Driven ESL Synthesis for Functional Trojan Fortification View

Symmetrical Protection of Ownership Right’s for IP Buyer and IP Vendor using Facial Biometric Pairing View